I. Field of the Disclosure
The technology of the disclosure relates generally to processor cores, and particularly to controlling power modes of processor cores.
II. Background
Processor-based computer systems can include one or more central processing units (CPUs) that each includes one or more processor cores for instruction execution. Each processor core includes hardware resources used to process an instruction through multiple pipeline stages. For example, processing an instruction in a pipeline may include fetching the instruction and decoding the instruction prior to sending the instruction to an execution unit, such as an arithmetic logic unit. Further, hardware resources of a processor core can be divided into separate portions known as “threads,” also referred to as “hardware threads.” The threads provide the processor core with the ability to process multiple instructions concurrently in parallel. More specifically, a thread within a processor core can process an instruction at the same time another thread within the same processor core processes a different instruction.
In this regard, processing instructions within a processor core contributes to the overall power consumption of the corresponding CPU. In an effort to conserve power, the CPU may employ a power control unit that is configured to control a power level of a processor core depending on the activity of the processor core. For example, the power control unit may provide a nominal power level to the processor core while at least one thread is in active status, so as to provide sufficient power to drive the hardware resources within the processor core to process instructions. However, if no threads are in active status in a processor core, the power control unit may power collapse the processor core to conserve power. In this manner, power consumption of the processor core, and its corresponding CPU, is conserved by providing nominal power to the processor core when the processor core has a thread in active status, and power collapsing the processor core when all threads are inactive.